1. Field of the Invention
The present invention relates, in general, to a semiconductor device and, more particularly, to improvement in the high integration of a semiconductor device as well as the operating speed thereof. Also, the present invention is concerned with a method for fabricating the semiconductor device.
2. Description of the Prior Art
CMOS (Complementary MOS) transistors are usually employed for the peripheral circuit of semiconductor memory devices because of their small power consumption and fast operating speed.
For construction of a CMOS transistor, an N-well and a P-well are first formed in a P type semiconductor substrate. Then, another P-well is formed in a predetermined portion of the N-well, to build a P type MOSFET and an N type MOSFET on the N-well and the P-well, respectively. The formation of the P-well in a predetermined portion of the N-well allows different voltages to be applied to the P type semiconductor substrate and the P-well because the N-well electrically isolates the P-well from the P type substrate.
In order to better understand the background of the present invention, a description of a conventional method for the fabrication of a semiconductor device will be given below, in connection with FIG. 1.
First, referring to FIG. 1A, there is shown an ion-implanting process taking advantage of an N-well mask. As shown in this figure, N type impurities are implanted into a predetermined area of a P type semiconductor substrate 1 covered with the N-well mask, to form an N-well region 2.
With reference to FIG. 1B, P type impurities are implanted into a predetermined area of the P type substrate 1 adjacent to an N-well region 2 and into the N-well region by use of a P-well mask, to, form a first P-well region 3A and a second P-well region 3B, both shallower than the N-well region, respectively.
With reference to FIG. 1C, element-isolating insulator films 4 are formed on the boundaries between the N-well region 2 and the first P-well region 3A and between the N-well region 2 and the second P-well region 3B by LOCOS (local oxidation of silicon) process, gate structures, each consisting of a gate oxide film 5 and a gate electrode 6, are formed on predetermined surfaces of the P-type substrate, and ion-implanting processes are carried out. For the N-well region P type impurities are implanted to give a source/drain electrode 8 and thus, obtain a P type MOSFET. On the other hand, N type impurities are implanted into the first P-well region 3A and the second P-well region 3B, to give a source/drain electrode 7 and thus, obtain N type MOSFETs.
This conventional method, however, has difficulty in achieving high integration of a semiconductor device since the element-isolating insulator films are formed along with bird's beaks by LOCOS process. In addition, the second P-well region within the N-well region contains many N type impurities as well as P type impurities, causing its N type MOSFET to be degraded in mobility.